1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to interconnect structures for connecting different device levels or chips.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are continuously decreased with the introduction of every new circuit generation, to provide currently available integrated circuits formed by volume production techniques with critical dimensions of 40 nm or less and having an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors has been an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs, GPUs (graphical processing units), memory devices and the like. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors, interconnect structures and the like, are typically formed in integrated circuits, as required by the basic circuit layout. Due to the decreased dimensions of the active circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density is improved, thereby providing the potential for incorporating additional functionality into a given chip area. For this reason, highly complex circuits based on CMOS technology have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
Although transistor elements are the dominant circuit element in highly complex integrated circuits based on high end CMOS techniques which substantially determine the overall performance of these devices, other components such as capacitors and resistors and in particular a complex interconnect system or metallization system may be required, wherein the size of these passive circuit elements may also have to be adjusted with respect to the scaling of the transistor elements in order to not unduly consume valuable chip area.
Typically, as the number of circuit elements, such as transistors and the like, per unit area may increase in the device level of a corresponding semiconductor device, the number of electrical connections associated with the circuit elements in the device level also grows, typically even in an over-proportional manner, thereby requiring complex interconnect structures which may be provided in the form of metallization systems including a plurality of stacked metallization layers. In these metallization layers, metal lines, providing the inner-level electrical connection, and vias, providing intra-level connections, may be formed on the basis of highly conductive metals, such as copper and the like, in combination with appropriate dielectric materials to reduce the parasitic RC (resistance capacitance) time constants, since, in sophisticated semiconductor devices, typically, signal propagation delay may be substantially restricted by a metallization system rather than the transistor elements in the device level. However, expanding the metallization system in the height dimension so as to provide the desired density of interconnect structures may be restricted by the parasitic RC time constants and the limitations imposed by the material characteristics of sophisticated low-k dielectrics. That is, typically, a reduced dielectric constant is associated with reduced mechanical stability of these dielectric materials, thereby also restricting the number of metallization layers that may be stacked on top of each other in view of yield losses during the various fabrication steps and the reduced reliability during operation of the semiconductor device. Thus, the complexity of semiconductor devices provided in a single semiconductor chip may be restricted by the capabilities of the corresponding metallization system and in particular by the characteristics of sophisticated low-k dielectric materials, since the number of metallization layers may not be arbitrarily increased.
For this reason, it has also been proposed to further enhance the overall density of circuit elements for a given size or area of a respective package by stacking two or more individual semiconductor chips, which may be fabricated in an independent manner, however, with a correlated design so as to provide in total a complex system, while avoiding many of the problems encountered during the fabrication process for extremely complex semiconductor devices on a single chip. For example, appropriately selected functional units, such as memory areas and the like, may be formed on a single chip in accordance with well-established manufacturing techniques including the fabrication of a corresponding metallization system, while the required other functional units, such as a fast and powerful logic circuitry, may be formed independently as a separate chip, wherein, however, respective interconnect systems may enable a subsequent stacking and attaching of the individual chips so as to form an overall functional circuit, which may then be packaged as a single unit. Similarly, different complex circuit portions, such as a CPU and a GPU, may be manufactured individually and may be subsequently combined into a stacked configuration. Thus, a corresponding three-dimensional configuration may provide increased density of circuit elements and metallization features with respect to a given area of a package, since a significant larger amount of the available volume in a package may be used by stacking individual semiconductor chips. Although this technique represents a promising approach for enhancing packing density and functionality for a given package size for a given technology standard, while postponing the problems of sophisticated CMOS techniques as these techniques may encounter fundamental physical limitations upon further device scaling, appropriate contact elements may have to be provided to enable the electrical connections of the individual semi-conductor chips in a reliable and well-performing manner.
To this end, it has been suggested to form through-hole vias through the substrate material of at least one of the chips so as to enable electrical contact to corresponding contact elements of a second semiconductor chip, while the metallization system of the first semi-conductor chip may further be available for connecting to other semiconductor chips or a package substrate and the like. Furthermore, appropriate contact structures, for instance including contact pads for receiving solder bump materials, bond wires and the like, are conventionally provided in order to establish the electrical connection between the individual semiconductor chips. As discussed above, in some cases, the circuits implemented in the individual semiconductor chips may have a moderately high degree of complexity, thereby also requiring an appropriate “inter chip” wiring system for exchanging the required signals between the individual semiconductor chips. For example, if a CPU core and an extended memory area are to be provided in different semiconductor chips, the corresponding address and control signals, as well as the data signals, have to be exchanged between the different semiconductor chips, thereby requiring efficient communication channels. Similarly, if such entities, such as a CPU and a GPU, are to be connected in a stacked configuration, a moderately complex wiring system is also required. Consequently, the corresponding contact structure may have a more or less complex design and may also require significant floor space, since conventional contact mechanisms based on wire bonding and/or direct bonding of appropriate contact bumps may not be scaled down in a desired manner. Consequently, significant advantages of increased transistor density obtained by providing a stacked semi-conductor configuration may be offset by the requirements of a complex “inter chip” contact structure.
Recently, concepts have been proposed for further increasing the packing density of integrated circuit devices by using specifically designed functional molecules to form molecular films having specifically designed characteristics. For example, organic base molecules may be appropriately designed so as to include functional groups for imparting the desired characteristics, such as conductivity and the like, to the molecules in order to act as conductors or even as switches when, for instance, the conductivity of these functional molecules may be changed on the basis of external stimuli, such as light, heat, electric fields, i.e., voltages, and the like. Consequently, great efforts are being made in order to develop molecular electronic systems based on molecular conductors and switchable elements, wherein, however, the combination of these components to form complex electronic circuits may still require extensive research. Furthermore, presently, it is not clear as to how these concepts may be implemented into volume production techniques so as to provide a cost efficiency that is comparable to present day sophisticated CMOS techniques.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.